1. Field of the Invention
The present invention relates to a switching power supply device, and particularly, a self-excited ringing choke converter-type switching power supply device.
2. Description of the Related Art
Currently, a switching power supply device is adopted as a power source for a device in many cases. Among switching power supply devices, a self-excited ringing choke converter (hereinafter referred to as RCC) has a simple configuration and is widely used as a low cost power supply device. FIG. 5 illustrates a typical configuration of an RCC. FIG. 6 illustrates a waveform of a gate voltage of a field-effect transistor (FET) Q1, and Vth is a threshold value of the gate voltage of the FET Q1.
In FIG. 5, the RCC includes a commercial power supply AC, a bridge diode DA1, and a smoothing capacitor C1. The smoothing capacitor C1 rectifies and smoothes the commercial power supply AC, and converts it to DC voltage. A high voltage side of DC voltage is denoted by VH, and a low voltage side of the DC voltage is denoted by VL. A transformer T1 includes a primary winding N1, a secondary winding N2, and a feedback winding NB. The RCC further includes a metal-oxide-semiconductor filed-effect transistor (MOSFET, hereinafter simply referred to as FET) Q1 as a main switching element, a diode D2, and a capacitor C4.
The FET Q1 is turned on and off intermittently. While the FET Q1 is turned on, current flows in the primary winding N1 of the transformer T1, and the transformer T1 stores energy. While the FET Q1 is turned off, the energy stored in the transformer T1 is released from the secondary winding N2 of the transformer T1, and the released energy is obtained by the diode D2 and the capacitor C4 as a secondary-side output DC voltage.
When the transformer T1 releases the stored energy from the secondary winding N2, the feedback winding NB generates ringing with an amplitude corresponding to a winding ratio to an output of the secondary winding N2. Voltage generated by the ringing is referred to as flyback voltage.
As illustrated with an arrow t601 in FIG. 6, the gate voltage of the FET Q1 rises by the ringing, and when the gate voltage reaches the threshold voltage Vth, the FET Q1 is turned on. When the FET Q1 is turned on, the feedback winding NB has a positive output. At this time, a capacitor C3 is charged by a current flowing in a resistance R5 and a phototransistor current in a photocoupler PC1.
As illustrated with an arrow t602 in FIG. 6, when voltage of both ends of the capacitor C3 exceeds threshold voltage of a transistor Q2, the transistor Q2 is turned on, and the FET Q1 is turned off. Therefore, the on-time period of the FET Q1 depends on charging current in the capacitor C3, that is, the current flowing in the resistance R5, and the phototransistor current of the photocoupler PC1. The phototransistor current in the photocoupler PC1 depends on a cathode current in a shunt regulator integrated circuit (IC) 1. Since the cathode current in the shunt regulator IC1 is controlled so that voltage of a control terminal to be a desired value, output voltage is fixed by changing the on-time period of the FET Q1. A voltage control of the secondary-side output DC voltage is executed by controlling the on-time period of the FET Q1.
Therefore, when power consumption is low, for example, when a device is in a standby state, the on-time period of the FED Q1 becomes short. Shortening of the on-time period may increase the number of switching of the FET Q1 per unit time, and increase switching loss. As a result, efficiency of the switching power supply device decreases.
About this problem of decrease of efficiency, for example, Japanese Patent No. 3386016 discusses a method for improving the efficiency in a configuration which can allow decrease of output voltage of a switching power supply device when the device becomes a standby state.
FIG. 7 illustrates a configuration for implementing the method discussed in Japanese Patent No. 3386016. Unlike the RCC in FIG. 5, an RCC in FIG. 7 includes an output voltage drop circuit including a transistor Q3 and resistances R11 and R12. The output voltage drop circuit is controlled by an input signal to a terminal SS.
In Japanese Patent No. 3386016, a winding ratio of the feedback winding NB to the secondary winding N2 of the transformer T1 is set as follows. When the energy stored in the transformer T1 is released from the secondary winding N2, ringing is generated in the secondary winding N2. The amplitude of the ringing is set according to whether the output voltage drop circuit functions or not. More particularly, when the output voltage drop circuit does not function, the gate voltage of the FET Q1 is set so as to exceed threshold voltage. When the output voltage drop circuit functions, the gate voltage of the FET Q1 is set so as not to exceed threshold voltage. Therefore, a gate voltage waveform of the FET Q1 becomes the waveform illustrated in FIG. 8 when the output voltage drop circuit functions. In addition, Vth in FIG. 8 is threshold voltage of the gate voltage of the FET Q1.
As illustrated with an arrow t801 in FIG. 8, the FET Q1 is turned on when the current flowing in from a starting resistance R1 is charged in the capacitor C2 and the gate voltage of the FET Q1 exceeds the threshold voltage Vth. Therefore, the number of switching of the FET Q1 decreases and decrease in the efficiency can be prevented.
A loss of the FET Q1 which is a main switching element includes a loss due to consumption of charge, which is stored in a capacity component between a drain and a source when the FET Q1 is off, by the FET Q1 at time of turning on and a switching loss at the time of turning off.
The loss at the time of the turning on can be acquired by multiplying a loss per one turning-on operation by oscillation frequency. If presuming that energy stored in the transformer T1 is entirely supplied to a load by flowing to the primary winding N1, the loss at the time of the turning off is described as follows.
The loss per one turning off operation is in proportion to a drain peak current Id of the FET Q1.
The turning off loss is acquired by multiplying a loss per one turning off operation by frequency.
The energy stored in the transformer T1 per one cycle of switching is in proportion to a square of the drain peak current Id of the FET Q1.
Power supplied to a load is acquired by multiplying the energy stored in the transformer T1 per one cycle of switching by frequency.
In the method discussed in Japanese Patent No. 3386016, a control of an output voltage value is performed by controlling the on-time period of the FET Q1. This control is performed by transmitting the cathode current in the shunt regulator IC1 to a primary side by the photocoupler PC1 and controlling a current flowing into the capacitor C3.
When a load becomes lower at the time of output voltage drop, the on-time period of the FET Q1 becomes shorter, but an off-time period of the FET Q1 is constant. Thus, even if the load changes, the number of switching of the FET Q1 per unit time is approximately constant. (Strictly, a frequency becomes quicker but does not affect the number of switching because the on-time period is shorter than the off-time period.)
Therefore, even when the load is lowered, the loss at the time of turning on does not change, and the drain peak current decreases in proportion to only a square root of the load. Thus, the loss increases because the turn-off time period is constant, and the efficiency decreases.